1. Field of the Invention
The present invention relates to computer systems, and more particularly, to a computer architecture for providing efficient communication and control of interrupts directed to multiprocessors on multiple buses.
2. Related Art
As a consequence of the rapidly evolving personal computer (PC) industry, high end PCs have migrated into high performance applications which were traditionally handled by minicomputers or mainframe computers. These high performance applications require interaction with many peripherals at high speeds as well as manipulation of enormous amounts of data to provide real time operation as perceived by a user.
As a result, multiple processors have been implemented in PC architectures to maximize speed by allocation of tasks and responsibilities which can be performed in parallel. In other words, the independent processors of a multiprocessor (MP) system execute instructions simultaneously via a multithread instruction set to concurrently process transactions.
As more and more processors are added to an MP system, the communication and control of interrupts becomes more complex and burdensome on an MP system. Interrupts are signals which prompt a central processing unit (CPU) to automatically and immediately execute a necessary special routine within a computer system.
Upon receipt of an interrupt, a CPU will follow an interrupt sequence. During the interrupt sequence, the CPU first completes the instruction currently being executed. Next, it saves all register values (for example, an instruction pointer (IP), code segment (CS), processor status word (PSW), and others) needed to return to the next instruction in a stack within the main memory or a special purpose register located in the CPU or elswhere. The interrupt routine then takes place. After the interrupt has been executed, the CPU returns to the program that it was originally executing via an instruction at the end of the interrupt routine which inserts the register values from the stack or special purpose register back into the CPU.
In an MP system, interrupts often originate from several different locations and accordingly are given special names. Some interrupts are "internal" interrupts. Internal interrupts are initiated by the state of the CPU or by an instruction. For example, typical internal interrupts would be one caused by a division by zero.
Other interrupts are "external" interrupts. External interrupts are caused by a signal being sent to the CPU from elsewhere in the computer system. An example of an external interrupt would be one caused by the need of an input/output (I/O) device to be serviced by the CPU.
Moreover, external interrupts can sometimes be divided into two types in MP systems having a complex network of interrupts: (1) "local" interrupts and (2) "global" interrupts. Local interrupts would be an interrupt originating locally with respect to the destination CPU, or in other words, an interrupt generated in the same subsystem. An example of a local interrupt would be an interrupt from a math coprocessor. In contrast, global interrupts originate in a subsystem other than the destination CPU. Examples of global interrupts are those generated from a user keyboard, a system timer, a disk drive controller, a video controller, a serial or parallel port, or the like.
Efficient communication and control of interrupts is critical for high performance MP systems. Specifically, global interrupts must be readily managed among all processors of an MP system where the processors are spread across several different buses.
In the conventional art, global interrupts are commonly controlled by a "system" interrupt controller. The controller may take the form of a single unit or multiple units working in concert. A typical system interrupt controller that can operate independently or in combination, for example, is an INTEL 8259 programmable interrupt controller (PIC). The INTEL 8259 interrupt controller is commercially available and is manufactured by the Intel Corporation, California, U.S.A.
In a usual interrupt protocol, the system interrupt controller communicates all interrupts to an arbitrary "default" CPU. The default CPU puts identifiable segments of data, which include instructions, into the shared main memory to specify the interrupt, the destination CPU, and the interrupt routine to be implemented by the destination CPU. The other processors in the MP system continuously access the shared main memory so as to monitor for queues or identifiers of the segments of data. The destination CPU then recognizes the interrupt and acts in accordance with the specified interrupt routine.
However, the foregoing conventional technique of global interrupt management is problematic in high performance MP systems with multiple buses. The default CPU often must temporarily stop execution of its own program in order to execute code related to the channelling of interrupts to the shared main memory.
Furthermore, excessive traffic exists on the buses between all of the CPUs and the shared main memory. Because of the numerous transactions that must take place between the CPUs and the main memory, the speed of the MP system as a whole is slower than optimum. Further, as a result of the reduced performance, the number of processors which may be interfaced to the MP system is more limited.
Another method known to be in the conventional art is called "interrupt snooping." Interrupt snooping has been suggested for MP systems where CPUs are situated on I/O cards having exclusive buses, such as the conventional extended industry standard architecture (EISA) bus or the conventional microchannel (MCA) bus. The I/O cards are plugged into, for instance, a fast system bus of the computer system, thereby forming a multiple bus system.
Interrupt snooping does not utilize the concept of a default CPU or any central location for generating and channelling interrupts. Interrupts are generated and received at each I/O card.
To implement the process of interrupt snooping, the bus master of each I/O card is equipped with an INTEL 8259 interrupt controller or an equivalent circuit(s) thereof. Interrupts from the interrupt controllers are masked from the components of the computer system that are not intended to receive interrupts. All of the bus masters monitor the system bus for interrupts corresponding to each and then direct the interrupts to local CPUs on its respective I/O card. Essentially, the entire responsibility for global interrupts is transferred from the computer system to the I/O cards.
However, the preceding interrupt management scheme is not ideal for a high performance MP system having multiple buses. The scheme requires that interrupts be managed on a bus by bus basis and that each bus have at least one interrupt transmission and reception mechanism. More specifically, if CPUs are added to the system bus where the I/O cards are interfaced, the added CPUs must duplicate interrupt logic, either in hardware or software, in order to send and receive interrupts to CPUs on the I/O cards. Moreover, standard interrupts from, for example, the system timer and/or the user keyboard, cannot be interfaced to the system bus without the addition of interrupt circuitry.